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1 of 15 102302 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of a ny device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the ds4000 digitally controlled temperature- compensated crystal oscillator (dc-tcxo) features a digital temperature sensor, one fixed- frequency temperature-compensated square-wave output (f 1 ), one programmable temperature- compensated square-wave output (f 2 ), and digital communication for frequency tuning (sda, scl). applications reference oscillators in pll circuits global positioning systems satcom telecom wireless base stations features aging 1.0ppm per year frequency stability 1.0ppm from -40c to +85c frequency versus supply stability of 1.0ppm per volt ? = base frequency is digitally tunable by 6.0ppm ? = one fixed-frequency output and one (n + 1) or 2(n + 1) division of the base frequency output temperature measurements from -40c to +85 c with 10-bit/+0.25c resolution and 3c accuracy 2-wire serial interface ordering information part temp range pin-package ds4000 a0/wbga 0c to +70c 12 bga ds4000a0-n/wbga -40c to +85c 12 bga ds4000cw/wbga 0c to +70c 12 bga ds4000cw-n/wbga -40c to +85c 12 bga ordering information continued at end of data sheet. pin configuration gnd osc bga 2 3 4 5 6 d c b a sda scl a 0 n.c. gnd 1 f 2 v osc v cc gnd gnd f 1 ds4000 digitally controlled (dc)-tcxo www.maxim-ic.com www.maxim-ic.com top view
ds4000 2 of 15 absolute maximum ratings voltage range on any pin relative to ground -0.3v to +6.0v storage temperature range -55 c to +85 c soldering temperature range see ipc/jedec j-std-020a (2x max) these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time can affect reliability. operating range range temp range v cc commercial 0c to +70c 5v 5% industrial -40c to +85c 5v 5% recommended dc operating conditions (over the operating range) parameter symbol conditions min typ max units supply voltage v cc notes 1, 2 4.75 5.0 5.25 v oscillator supply voltage v osc notes 1, 2 4.75 5.0 5.25 v input logic high v ih note 1 2.2 v cc + 0.3 v input logic low v il note 1 -0.3 +0.8 v dc electrical characteristics (over the operating range) parameter symbol conditions min typ max units active supply current i cc notes 3, 4 1.5 2 ma active oscillator supply current i osc notes 3, 4 3.5 5.5 ma output logic high 2.4v i oh note 1 -1 ma output logic low 0.4v i ol note 1 4 ma input leakage i li 1 a i/o leakage i lo 1 a temperature conversion time t convt note 3 250 300 ms note 1: all voltages are referenced to ground. note 2: for 10% operating range, contact factory. note 3: typical values are at +25 c and nominal supplies. note 4: these parameters are measured with the outputs disabled.
ds4000 3 of 15 ac electrical characteristics: tcxo (over the operating range) parameter symbol condition min typ max units output frequency f 1 f 2 cmos (note 5) 10 20 mhz frequency stability vs. temperature ? f/t a ppm voltage ? f/v ppm/v aging ? f/yr -1.0 +1.0 ppm/yr f 1 , f 2 rise and fall time, 10% to 90% t r , t f 4 ns max output capacitive load c l 10 pf duty cycle t w / t 40 50 60 % phase noise f1 output, 10khz n note 6 -130 dbc/hz note 5: f 1 is the base frequency as defined by the package markings. f 2 is a programmable frequency output. the output frequency of f 2 is derived from the base frequency, f 1 , by programming the f 2 frequency select register and duty cycle (dc) bit in the tcxo control register. the minimum output frequency is f 1 / (2 8 + 1) with dc = 0 and f 1 / [2 x (2 8 + 1)] with dc = 1. note 6: 10mhz, 5v, +25c with one of the two outputs enabled.
ds4000 4 of 15 ac electrical characteristics: 2-wire serial interface (v cc = 4.75 to 5.25v, t a = -40 c to +85 c) parameter symbol condition min typ max units fast mode 0 400 scl clock frequency f scl standard mode 0 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode 4.7 s fast mode (note 7) 0.6 hold time (repeated) start condition t hd:sta standard mode (note 7) 4.0 s fast mode 1.3 low period of scl clock t low standard mode 4.7 s fast mode 0.6 high period of scl clock t high standard mode 4.0 s fast mode 0.6 setup time for a repeated start condition t su:sta standard mode 4.7 s fast mode (note 8) 0 0.9 data hold time t hd:dat standard mode (note 8) 0 0.9 s fast mode (note 9) 100 data setup time t su:dat standard mode (note 9) 250 ns fast mode (note 9) 20 + 0.1c b 300 rise time of both sda and scl t r standard mode (note 9) 20 + 0.1c b 1000 ns fast mode (note 10) 20 + 0.1c b 300 fall time of both sda and scl t f standard mode (note 10) 20 + 0.1c b 1000 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 s capacitive load for each bus line c b note 10 400 pf input capacitance c i 5 pf note 7: after this period, the first clock pulse is generated. note 8: the maximum t hd:dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. note 9: a fast-mode device can be used in a standard mode system, but the requirement t su:dat >250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the s cl signal, it must output the next data bit to the sda line t rmax + t su:dat (1000 + 250 = 1250ns) before the scl line is released. note 10: c b : total capacitance of one bus line in pf.
ds4000 5 of 15 figure 1. timing diagram pin descriptions pin name function 1, 11, 12 gnd ground. dc power is provided to the device on these pins. 2 n.c. no connection 3 gnd osc oscillator ground. dc power is provided to the oscillator on these pins. 4 a 0 2-wire slave address input. this pin is used to configure the slave address. 5 sda 2-wire serial-data input/output. sda is the input/output pin for the 2-wire serial interface. the sda pin is open drain and requires an external pullup resistor. 6 scl 2-wire serial-clock input. scl is used to synchronize data movement on the serial interface. the scl pin is open drain and requires an external pullup resistor. 7 f 2 dc-tcxo frequency output 8 v cc power supply. dc power is provided to the device on these pins. 9 f 1 dc-tcxo frequency output 10 v osc oscillator power supply. dc power is provided to the oscillator on these pins.
ds4000 6 of 15 detailed description the ds4000 digitally controlled temperature-compensated crystal oscillator (dc-tcxo) features a digital temperature sensor, one fixed-frequency temperature-compensated square-wave output (f 1 ), one programmable temperature-compensated square-wave output (f 2 ), and digital communication for frequency tuning (sda, scl). figure 2. block diagram 2-wire serial interface sda scl digital temperature sensor temperature- compensated crystal oscillator f 2 f 1 v cc gnd ds4000 v osc gnd osc a0
ds4000 7 of 15 temperature-compensated crystal oscillator the ds4000 can either function as a standalone tcxo or as a digitally controlled tcxo. when used as a standalone tcxo, the only requirements needed to function properly are power, ground, and an output. however, the 2-wire interface must be used to tune (push and pull) the crystal. the ds4000 is capable of supplying two different outputs, f 1 and f 2 . 1) f 1 is the base frequency of the crystal unit inside of the device. the output type is a cmos square wave. 2) f 2 is a programmable frequency output. the frequency select register can program this output to an integer division of the base (f 1 ) frequency. the duty cycle (dc) bit determines if the output is an n + 1 or a 2(n + 1) division of f 1 . f 2 frequency select register (fsr) (5dh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 f 2 = f 1 / (fsr value + 1); with dc = 0 f 2 = f 1 / [2 x (fsr value + 1)]; with dc = 1 tcxo control register (60h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x f 2 oe f 1 oe f t dc dc, duty cycle bit: if 50% duty cycle is desired, then this bit must be set to logic 1. the default condition at power-up is logic 0. f t : this bit must be programmed by the user to a 0. f 1 oe, f 1 output enable bit: this bit allows the user to disable/enable the f 1 output. f 2 oe, f 2 output enable bit: this bit allows the user to disable/enable the f 2 output.
ds4000 8 of 15 digital tuning the base crystal frequency when using the 2-wire interface for tuning the base frequency, the frequency tuning register is used. the frequency tuning register contains two?s complement data. the data is used to add or subtract an offset from the crystal loading register. when the tuning register is programmed with a value, the next temperature-update cycle sums the programmed value with the factory-compensated value. this allows the user/system to digitally control the base frequency by a microcontroller using the 2-wire protocol. frequency tuning register (66h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sign fo6 fo5 fo4 fo3 fo2 fo1 fo0 fos[6:0], frequency offset: these bits are used to tune the base crystal frequency. each bit represents approximately 0.05ppm and, therefore, for a value of 07fh, pushes or pulls the base frequency by approximately 6.35ppm. sign, sign bit: this bit is used to determine whether to add or subtract the frequency offset from the crystal loading. table 1. frequency tuning relationship calculated frequency offset (ppm) digital data (binary) digital data (hex) +6.35 0111 1111 7fh +5.0 0110 0100 64h +3.3 0100 0010 42h +1.2 0001 0111 17h +0.05 0000 0001 01h 0.0 0000 0000 00h -0.05 1111 1111 ffh -1.2 1110 1000 e8h -3.3 1011 0011 b3h -5.0 1001 1100 9ch -6.35 1000 0000 80h
ds4000 9 of 15 digital temperature sensor the digital temperature sensor provides 10-bit temperature readings that indicate the temperature of the device. temperature readings are communicated from the ds4000 over a 2-wire serial interface. no additional components are required. the ds4000 has an external address bit that allows a user to choose the slave address from two possible values. the factory-calibrated temperature sensor requires no external components. upon power-up, the ds4000 starts performing temperature conversions with a resolution of 10 bits (+0.25c resolution). following an 8-bit command protocol, temperature data can be read over the 2-wire interface. the host can periodically read the value in the temperature register, which contains the last completed conversion. as conversions are performed in the background, reading the temperature register does not affect the conversion in progress. reading temperature the ds4000 measures temperature through the use of an on-chip temperature-measurement technique with an operation range from 0c to +70c (commercial) or -40c to +85c (industrial). the device performs continuous conversions with the most recent result being stored in the temperature register. the digital temperature is retrieved from the temperature register using the read temperature command, as described in detail in the following paragraphs. table 2 shows the exact relationship of output data to measured temperature. the data is transmitted serially over the 2-wire serial interface, msb first. the msb of the temperature register contains the ?sign? (s) bit, denoting whether the temperature is positive or negative. for fahrenheit usage, a lookup table or conversion routine must be used. temperature/data relationship (unit = c) msb ( 64h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 lsb ( 65h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2 -1 2 -2 0 0 0 0 0 0 table 2. temperature/data relationship temperature (c) digital output (binary) digitaloutput (hex) +85 0101 0101 0000 0000 5500h +75 0100 1011 0000 0000 4b00h +0.5 0000 0000 1000 0000 0080h 0 0000 0000 0000 0000 0000h -0.5 1111 1111 1000 0000 ff80h -20 1110 1100 0000 0000 ec00h -40 1101 1000 0000 0000 d800h note: internal power dissipation raises the temperature above the ambient. the delta between ambient and the die temperature depends on power consumption, pc board layout, and airflow.
ds4000 10 of 15 read temperature command this command reads the last temperature conversion result from the temperature register in the format described in the reading temperature section. if an application can accept temperature resolutions of +1.0c, then the master can read the first data byte and follow with a nack and stop. for higher resolution, both bytes must be read. table 3. command set instruction function protocol 2-wire bus data after issuing protocol frequency select register (note 1) defines f 2 output frequency 5dh read or write 1 data byte tcxo control register (note 1) enables/disables f 1 and f 2 ; sets duty cycle of f 2 60h read or write 1 data byte read temperature (note 2) reads 10-bit temperature register 64h read 1 or 2 data bytes frequency tuning register (note 2) digitally adds/subtracts an offset from oscillator 66h read or write 1 data byte note 1: the slave does not increment the internal address pointer between instructions. the address pointer must be reinitialized afte r each access. note 2. if the user only desires 8-bit thermometer readings, the master can read one data byte, and follow with a nack and stop. if hi gher resolution is required, both bytes must be read.
ds4000 11 of 15 2-wire serial interface the ds4000 supports a bidirectional 2-wire serial bus and data transmission protocol. the bus must be controlled by a master device, which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds4000 operates as a slave on the 2-wire bus. the ds4000 works in a regular mode (100khz clock rate) and a fast mode (400khz clock rate), which are defined within the bus specifications. connections to the bus are made by the open-drain i/o signals sda and scl. the following bus protocol has been defined (figure 3): data transfer can be initiated only when the bus is not busy. during data transfer, the data signal must remain stable whenever the clock signal is high. changes in the data signal while the clock signal is high are interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock signals remain high. start data transfer : a change in the state of the data signal, from high to low, while the clock line is high, defines the start condition. stop data transfer: a change in the state of the data signal, from low to high, while the clock line is high, defines the stop condition. data valid : the state of the data signal represents valid data when, after a start condition, the data signal is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is required to generate an acknowledge after reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the serial data (sda) signal during the acknowledge clock pulse in such a way that the sda signal is stable low during the high period of the acknowledge- related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end-of-data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data signal high to enable the master to generate the stop condition.
ds4000 12 of 15 figure 3. data transfer on 2-wire serial bus data transfer figures 4 and 5 detail how data transfer is accomplished on the 2-wire bus. depending on the r/ w bit in the transmission protocols as shown, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the slave address). the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. 123-56789 sda scl start condition stop condition or repeated start condition 89 3-7 12 ack ack repeated if more bytes are transferred msb slave address r/w bit acknowledgement signal from receiver acknowledgement signal from receiver
ds4000 13 of 15 slave address the slave address is the first byte received following the start condition generated by the master device. the address byte consists of a 7-bit slave address and the r/ w direction bit. the ds4000 slave address is set to 100010a 0 , where a 0 is externally hardwired to a high or low state. this allows design flexibility to set the slave?s address to one of two possible address locations. the last bit following the slave address is the direction bit (r/ w ) and defines the operation to be performed by the master, transmit data (r/ w = 0), or receive data (r/ w = 1). following the start condition, the ds4000 monitors the sda bus by checking the slave address being transmitted. upon receiving the proper slave address and r/ w bit, the slave device outputs an acknowledge signal on the sda line regardless of the operation mode. the ds4000 can operate in the following two modes: 1) slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by the hardware after reception of the slave address and direction bit (figure 4). 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the ds4000 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer (figure 5). figure 4. data write: slave receiver mode < slave address > r/w < data address > < data (n)> s 100010a 0 0 a xxxxxxxx a xxxxxxxx a p s = start a = acknowledge p = stop figure 5. data read: slave transmitter mode < slave address > r/w s 100010a 0 1 a xxxxxxxx a xxxxxxxx a xxxxxxxx a xxxxxxxx a p s = start a = acknowledge p = stop a = not acknowledge
ds4000 14 of 15 ordering information part temp range pin-package top mark frequency designator (mhz) ds4000a0/wbga 0c to +70c 12 bga ds4000a0 10.00000 ds4000a0-n/wbga -40c to +85c 12 bga ds4000a0-n 10.00000 ds4000cw/wbga 0c to +70c 12 bga ds4000cw 12.80000 ds4000cw-n/wbga -40c to +85c 12 bga ds4000cw-n 12.80000 ds4000d0/wbga 0c to +70c 12 bga ds4000d0 13.00000 ds4000d0-n/wbga -40c to +85c 12 bga ds4000d0-n 13.00000 ds4000ec/wbga 0c to +70c 12 bga ds4000ec 14.31818 ds4000ec-n/wbga -40c to +85c 12 bga ds4000ec-n 14.31818 ds4000g0/wbga 0c to +70c 12 bga ds4000g0 16.00000 ds4000g0-n/wbga -40c to +85c 12 bga ds4000g0-n 16.00000 ds4000gf/wbga 0c to +70c 12 bga ds4000gf 16.38400 ds4000gf-n/wbga -40c to +85c 12 bga ds4000gf-n 16.38400 ds4000gw/wbga 0c to +70c 12 bga ds4000gw 16.80000 ds4000gw-n/wbga -40c to +85c 12 bga ds4000gw-n 16.80000 ds4000ki/wbga 0c to +70c 12 bga ds4000ki 19.44000 ds4000ki-n/wbga -40c to +85c 12 bga ds4000ki-n 19.44000
ds4000 15 of 15 package information note: the bga is solder-masked defined.

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